1. Field of the Invention
The present invention generally relates to a charge pump circuit, and more particularly, to a charge pump circuit which can reduce voltage spike.
2. Description of Related Art
Various voltage source levels are usually required in an electronic apparatus, thus, a charge pump circuit is usually employed to generate voltage sources of different levels. Plural charge pump circuits are applied in power supply circuit of display panel.
FIG. 1 illustrates a conventional charge pump circuit. Referring to FIG. 1, the charge pump circuit 100 includes a switch control circuit 102, switches 104˜107, a capacitor CS, and a capacitor CL. The conventional switch control circuit 102 generates two clock signals ph11 and ph12 which have non-overlapping duty cycles for controlling the on/off of the switches 104˜107, so that the charge pump circuit 100 can provide an output voltage Vo different from an input voltage Vi.
FIG. 2 is a waveform of clock signals of the switch control circuit 102 in FIG. 1. When the clock signal ph11 is enabled, the switches 104 and 105 are turned on, and the capacitor CS is charged; and when the clock signal ph12 is enabled, the switches 106 and 107 are turned on, and the capacitor CS is discharged while the capacitor CL is charged.
To describe the disadvantage of the conventional charge pump circuit here, it is assumed that the voltage originally spanning over the capacitor CS or CL is V1, a voltage about to span over one of the capacitors is V2, and it is assumed that in a first case, the voltages V1 and V2 are close to each other, while in a second case, the voltages V1 and V2 are very different. For instance, when the voltage V2 spans over the capacitor CS or CL, a voltage spike is produced instantaneously due to the voltage sag (V1>>V2) or voltage swell (V1<<V2) over the capacitor. Thus, according to foregoing assumption, the voltage spike in the second case is greater than the voltage spike in the first case.
Referring to FIG. 2 again, in the conventional charge pump circuit, the transition slope of the clock signal ph11 or ph12 from a logic low level to a logic high level is vertical, and the transition slope thereof from a logic high level to a logic low level is also vertical. Besides, since the actions of the switches 104˜107 are controlled by the clock signal ph11 or ph12, the switches 104˜107 are turned on/off quickly, so that the potential difference of the voltages over the capacitors CS and CL is always in transient changes, and accordingly continuous voltage spikes are produced.
The disadvantages of voltage spike in the application of the conventional charge pump circuit will be described herein. When a conventional charge pump circuit is applied to a small-size display panel, voltage spikes are produced at instances when switches are enabled, so that the common voltage in the display panel is disturbed and accordingly the pixel quality of the display panel is affected. In addition, if the conventional charge pump circuit is applied to a large-size display panel, the working frequencies of the clock signals ph11 and ph12 are usually increased in order to reach certain driving capability due to insufficient pixel driving capability of the conventional charge pump circuit. However, such increase in working frequencies of the clock signals may cause increase in voltage spikes and coupling between voltage spikes and some of the pixel data, therefore incorrect pixel data will be produced and both grey scale performance and image quality of the display panel will be affected.
Moreover, currently, the trend of designing a chip is towards minimization in die size. However, when applied to a display panel, the working frequency of the charge pump circuit has to be increased due to insufficient driving capability of the minimized charge pump circuit, and such increase in working frequency may produce more continuous voltage spikes and accordingly affect the display quality of the display panel.